14th International
SoC Design Conference

November 5 ~ 8, 2017
GRAND HILTON HOTEL, Seoul, Korea

Keynote Speakers

November 6 (Monday), 2017

[Keynote #1] 10:15 AM~11:00 AM

Title : High Performance Memory Trends and Prospects for AI

Seong Jin Jang
Executive Vice President, DRAM Product & Technology, Samsung Electronics, Korea

Biography

Seong Jin Jang received the B.S. degree in electronic engineering from Kyung Book University, Daegu, Korea, in 1987, and the M.S. degree in electrical engineering from the Korea Advanced Institute of Science and Technology, Seoul, in 1990. He joined LG Semicon Corporation, Ltd., Seoul, in 1990, where he was engaged in DRAM design division. Since 2000, he has worked for Samsung Electronics as a Executive Vice President of the DRAM Product & Technology Division.

Abstract

We have been able to continuously enhance not only process scaling, but also speed, power, and density scaling since DRAM has appeared in 1971. As we move towards a data driven world, the role of DRAM is predicted to have greater importance in speed, power, density and scaling; and a new paradigm shift breaking the wall between processors and memories is more likely than ever.

The key drivers of the fourth industrial revolution include AI and 5th generation wireless system. Semiconductor devices are to especially play a key role in AI. AI, often represented by AlphaGo, has similar data processing speed to human, but further enhancement is needed in regards to connecting speed and power efficiency.

AI performance is highly dependent on memory bandwidth, thus Bandwidth improvement is absolutely necessary. This can be accomplished by further improvement of power efficiency and form factor like HBM. Efforts have been made to create products with low power, high speed, and high bandwidth.

In particular, processing in memory is expected to become an efficient data processing product between processors and memory devices. We hope for its continuous research of industry and academia.

[Keynote #2] 11:00 AM~11:45 AM

Title : Implications brought in by the Coming Semiconductor Technologies

Antun Domic
Chief Technology Officer, Synopsys, Inc., USA

Biography

Antun Domic is Synopsys' newly appointed CTO, As the company's technical spokesperson, he will focus on aligning our advanced silicon roadmaps, driving our performance/low-power differentiation, and optimizing engineering execution across all business units. He previously served as executive vice president and general manager of the Synopsys Design Group, for which he led the development of the company's implementation and analog/mixed-signal product lines. Prior to joining Synopsys in 1997, Antun worked at Cadence Design Systems; at the Mircoprocessor Group of Digital Equipment Corporation in Huson, Mass.; and at the Massachusetts Institute of Technology(MIT) Lincoln Laboratories in Lexington, Mas. Antun holds a B.S. from the University of Chile in Santiago and a Ph.D. in Mathematics from MIT.

Abstract

We are now in late 2017. What is happening with the advanced semiconductors technologies and what can we expect to see in the next few years? We can say 10nm FinFET semiconductor technologies are ramping up in production. Samsung had indicated production status, and very recently the largest standalone semiconductor fab, TSMC, indicated it is recording revenue from their 10nm offer. At the same time, fabs are already introducing their 7nm technologies. Looking into what comes next, whether the next technology is called 5nm or not, we can say a few things. First, it seems clear the FinFET will be the prevalent device. Second, the current view from the fabs is that EUV will be used for wafer processing on some layers.
Sheer complexity will continue to hit unprecedented levels as it has been the norm with the progress of Moore's Law. One clear implication is that the overall functional verification process will consume large resources. But what will be very different as we look ahead at 5nm?
In our opinion, the complexity of physical design will increase very significantly. While one looks forwards to the fact that the use of EUV should make many of the double patterning and coloring layout rules simpler, other aspects will become much harder. One area of concern is the overall standard cell placement, as interactions between cells become much more complex introducing multiple new rules. If we couple these with the restrictions on router access to cell

pins, and the greater current densities we expect, we can predict much work in EDA will be needed. One can pick many other examples telling us that physical design faces real challenges.
The "ramp up to volume" process becomes more complicated. As experiments such as test chips used to evaluate technologies are more expensive, some steps where a chip team may do something differently (metal fills, for instance) will require deeper understanding of the many interactions. Many aspects of Design and Technology Co-Optimization (DTCO), up to block layout trials, are becoming a reality to insure the introduction of new technologies will not cause late surprises.

At the established technology nodes, unlike in the past, older nodes are not discontinued. On the contrary, not only the number of active technology nodes in production is increasing, but more than 90% of design starts in 2016 were at 45/40 nm and above, accounting for more than 50% of wafer production by area.
Production volumes dictate which applications rush to the newest technology node. An alternative to take advantage of previous designs is the use of 2.5D-IC and eventually 3D-IC integration techniques. It is hard to think of digital and true analog/mixed-signal blocks co-existing on the same die at 7 or 5nm. There have been remarkable successes with 2.5D-IC approaches, but mostly for advanced designs (such as HBM cubes). Further work is needed to make design flows much simpler and "standard" so their use becomes much more common.

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