14th International
SoC Design Conference

November 5 ~ 8, 2017
GRAND HILTON HOTEL, Seoul, Korea

Invited Special Sessions

November 6, 2017

[SS #1] 13:30~14:45

Session Title : Design, Analysis and Tools for Integrated Circuits and Systems (DATICS)
Organizer : Ka Lok Man (Xi'an Jiaotong-Liverpool University, Suzhou, China)

Abstract

DATICS special sessions were initially created by a network of researchers and engineers both from academia and industry in the areas of Design, Analysis and Tools for Integrated Circuits and Systems (DATICS). The proposed DATICS-ISOCC'17 special session will focus on emerging Circuits and Systems (CAS) topics that will strongly lead human life revolutions, especially in CMOS technologies, communication technologies and biomedical technologies. Human life revolutions come along with economic opportunities. The market for these emerging topics is also forecast to grow to a multi-billion dollar market in the coming decade.
The special session will highlight the potential and current developments of these CAS topics, along with pressing challenges. The proposed session is coherent and complementary to the conference theme and areas of interest of ISOCC. The main target of DATICS-ISOCC'17 is to bring together engineering researchers and people from industry to exchange theories, ideas, techniques and experiences.

[SS #2] 15:00~16:15

Session Title : Bio Sensing, Bio Mimicking, and Bio Inspired Circuits and Systems
Organizer : Prof. Kyeong-Sik Min (Kookmin Univ., Seoul, Korea)

Abstract

A building block computing system is consisting of multiple chips connecting with inductive coupling wireless through chip interconnect. Like building a chip by stacking LEGO blocks, various types of systems can be built by stacking various types of chips. For development of such systems, various techniques: inductive coupling wireless through chip interface, low power circuit technologies, autonomous interconnection network architectures and building block OS. In this session, various techniques in the project is introduced.

[SS #3] 16:45~18:00

Session Title : : Multi-core system for AI
Organizer : Hideharu Amano (Keio University, Tokyo, Japan)

Abstract

A building block computing system is consisting of multiple chips connecting with inductive coupling wireless through chip interconnect. Like building a chip by stacking LEGO blocks, various types of systems can be built by stacking various types of chips. For development of such systems, various techniques: inductive coupling wireless through chip interface, low power circuit technologies, autonomous interconnection network architectures and building block OS. In this session, various techniques in the project is introduced.

November 7, 2017

[SS #4] 9:30~10:45

Session Title : CMOS image sensors
Organizer : Seong-Jin Kim (UNIST, Ulsan, Korea)

Abstract

CMOS image sensors are indispensable components in mobile devices such as smartphones and digital cameras, and their applications are expanding to biomedical, automotive, and internet of things(IoT). This session includes recent advances in CMOS imagers. Two papers present the edge detection by a delta-readout scheme and the motion/gesture recognition operated at extremely low power, which are crucial features for the human-computer interface. The next paper shares the state-of-the-art fluorescence-lifetime imaging based on a lock-in pixel technique. A low noise pixel architecture configuring a common-source amplifier in a pixel is presented, and finally the session concludes with a paper reporting an always-on image sensor for IoT applications.

[SS #5] 11:00~12:15

Session Title : Computational Devices, Circuits and Systems
Organizer : Minkyu Je (KAIST, Daejeon, Korea)

Abstract

Session Abstract: In this special session, leading-edge research works on the circuits and systems for various sensors as well as the circuit techniques for sensor node SoCs are presented. The presented sensor applications include EEG sensors, finger print sensors, accelerometers, and neural probes.

[SS #6] 13:45~15:00

Session Title : : Error Correction Coding Architecture
Organizer : Youngjoo Lee (POSTECH, Pohang, Korea)

Abstract

As the demand of data integrity has increased rapidly in recent years, the advanced forward error correction (FEC) schemes have been continuously proposed to recover erroneous data without using retransmitting protocols. Considering the recent ultra-high-speed but energy-starving digital systems, traditional massive-parallel FEC architectures are no longer suitable for the contemporary systems due to their impractical hardware complexities. To share the latest innovations on FEC encoders and decoders, in this special session, we invite original research and review articles covering FEC design-level challenges for practical applications including wireless communications, wireline techniques, and even storage devices.

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