14th International
SoC Design Conference

November 5 ~ 8, 2017

Tutorial (Sunday, November 5, 2017)

November 5 (Sunday), 2017

[Tutorial 1-1] 13:00~14:30

Title : Smart Sensor Microsystems: Application-Dependent Integration Approaches

Minkyu Je
Ph.D., Associate Professor, KAIST, Korea


Minkyu Je received the M.S. and Ph.D. degrees, both in Electrical Engineering and Computer Science, from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 1998 and 2003, respectively. In 2003, he joined Samsung Electronics, Giheung, Korea, as a Senior Engineer and worked on multi-mode multi-band RF transceiver SoCs for GSM/GPRS/EDGE/WCDMA standards. From 2006 to 2013, he was with Institute of Microelectronics (IME), Agency for Science, Technology and Research (A*STAR), Singapore. He worked as a Senior Research Engineer from 2006 to 2007, a Member of Technical Staff from 2008 to 2011, a Senior Scientist in 2012, and a Deputy Director in 2013. From 2011 to 2013, he led the Integrated Circuits and Systems Laboratory at IME as a Department Head. In IME, he led various projects developing low-power 3D accelerometer ASICs for high-end medical motion sensing applications, readout ASICs for nanowire biosensor arrays detecting DNA/RNA and protein biomarkers for point-of-care diagnostics, ultra-low-power sensor node SoCs for continuous real-time wireless health monitoring, and wireless implantable sensor ASICs for medical devices, as well as low-power radio SoCs and MEMS interface/control SoCs for consumer electronics and industrial applications. He was also a Program Director of NeuroDevices Program under A*STAR Science and Engineering Research Council (SERC) from 2011 to 2013, and an Adjunct Assistant Professor in the Department of Electrical and Computer Engineering at National University of Singapore (NUS) from 2010 to 2013. He was an Associate Professor in the Department of Information and Communication Engineering at Daegu Gyenogbuk Institute of Science and Technology (DGIST), Korea from 2014 to 2015. Since 2016, he has been an Associate Professor in the School of Electrical Engineering at Korea Advanced Institute of Science and Technology (KAIST), Korea.

His main research areas are advanced IC platform development including smart sensor interface ICs and ultra-low-power wireless communication ICs, as well as microsystem integration leveraging the advanced IC platform for emerging applications such as intelligent miniature biomedical devices, ubiquitous wireless sensor nodes, and future mobile devices. He is an author of 5 book chapters, and has more than 260 peer-reviewed international conference and journal publications in the areas of sensor interface IC, wireless IC, biomedical microsystem, 3D IC, device modeling and nanoelectronics. He also has more than 40 patents issued or filed. He has served on the Technical Program Committee and Organizing Committee for various international conferences, symposiums and workshops including IEEE International Solid-State Circuits Conference (ISSCC), IEEE Asian Solid-State Circuits Conference (A-SSCC) and IEEE Symposium on VLSI Circuits (SOVC).


With the future filled with a trillion sensors on the way, there is a large variety in the forms of smart sensors for different applications existing or emerging, such as environmental monitoring, smart grid, green transportation, smart home and building, wearables, implants, and so on. The applications of sensors and corresponding use scenarios define desired form factors, operation frequencies and durations, energy sourcing and management strategies, communication distances and data rates, as well as control interfaces and protocols, leading to significantly different microsystem structures and integration approaches eventually. In this talk, the application dependence of the microsystem structures and integration approaches are investigated, along with several examples of the smart sensor microsystem integration across different applications introduced. While we find the optimally crafted system designs and integration strategies can draw the maximum out of currently available technologies on one hand, the study on the other hand reveals the limitations, challenges, and bottlenecks of the technologies to overcome for a leap to the next stage of the sensor world.

[Tutorial 1-2] 14:45~16:15

Title : Ultra-low Power/Energy SRAM Design for Internet-of-Things

Tony Tae-Hyoung Kim
Ph.D., Associate Professor, NTU, Singapore


Tony Tae-Hyoung Kim received the B.S. and M.S. degrees in electrical engineering from Korea University, Seoul, Korea, in 1999 and 2001, respectively. He received the Ph.D. degree in electrical and computer engineering from University of Minnesota, Minneapolis, MN, USA in 2009. From 2001 to 2005, he worked for Samsung Electronics where he performed research on the design of high-speed SRAM memories, clock generators, and IO interface circuits. In 2007 ~ 2009 summer, he was with IBM T. J. Watson Research Center and Broadcom Corporation where he performed research on circuit reliability, low power SRAM, and battery backed memory design, respectively. On November 2009, he joined Nanyang Technological University where he is currently an associate professor.

He received "Best Demo Award" ay APCCAS2016, "Low Power Design Contest Award" at ISLPED2016, best paper awards at 2014 and 2011 ISOCC, "AMD/CICC Student Scholarship Award" at IEEE CICC2008, Departmental Research Fellowship from Univ. of Minnesota in 2008, "DAC/ISSCC Student Design Contest Award" in 2008, "Samsung Humantec Thesis Award" in 2008, 2001, and 1999, and "ETRI Journal Paper of the Year Award" in 2005. He is an author/co-author of +110 journal and conference papers and has 17 US and Korean patents registered. His current research interests include low power and high performance digital, mixed-mode, and memory circuit design, ultra-low voltage circuits and systems design, variation and aging tolerant circuits and systems, and circuit techniques for 3D ICs. He serves as an Associate Editor of IEEE Transactions on VLSI Systems. He is an IEEE senior member and the Chair of IEEE Solid-State Circuits Society Singapore Chapter. He has served numerous conferences as a committee member.


Recently, various ultra-low power applications such as Internet-of-Things (IoT), wearable devices, and biomedical devices have emerged opening up a new domain of integrated circuits design. In these applications, ultra-low voltage circuit techniques for improving the power and energy efficiencies have been the main research focus. One of the most challenging functional blocks in ultra-low power systems is memory where SRAMs are dominantly employed. Since SRAMs occupy majority of the power in those systems, design of ultra-low power SRAMs is a critical task for power and energy efficiencies. One of the most popular SRAM design methodology for ultra-low power applications is using aggressively scaled supply voltage. However, this deteriorates various SRAM design parameters such as stability, sensing margin, write margin, etc. Various techniques for ultra-low voltage SRAMs have been reported to tackle the limitations at ultra-low voltage operation. This tutorial will provide the basics in ultra-low voltage SRAMs followed by the trend in various state-of-the-art ultra-low voltage SRAMs. More detailed ultra-low voltage SRAM design works developed by the author's group will also be explained. Finally, we will discuss future directions in ultra-low voltage SRAMs including various emerging non-volatile memory devices such as STTRAM, RRAM, etc.

[Tutorial 1-3] 16:30~18:00

Title : Secure SOC based on Physical Unclonable Functions

Jein Yu
Ph.D., Senior Engineer, ICTK Co. Ltd., Korea


Jein Yu, Ph.D. has been senior engineer position at ICTK since 2015 with responsibility of project planning and security solution developing. For the past two years, he was dedicated on developing PUF based H/W security solution. Prior to joining ICTK, Yu was a senior engineer position for Samsung electronics. During his 4 years at Samsung, Yu spent time researching the new technologies for smartphone, smart TV and so on.

Jein Yu received a Ph. D degree in electrical engineering from KAIST, Daejeon, Korea in 2012


A variety of methods for implementing physical unclonable function (PUF) in a semiconductor chip have been extensively studied because it is widely accepted that PUFs are very promising in the fields of identification, authentication or key generation in radio frequency identification (RFID) tags, smart card ICs, IP protection, and so on. In this session, a novel approach for very stable physical unclonable function (PUF) is presented based on randomly generated via-hole formation using standard CMOS process. Recently, various types of PUF technologies have been presented. However, because of the low reliability, which is the major drawback of conventional PUFs, complicated post processing to reduce bit error rate (BER) is indispensable. To achieve 0% BER, VIA-PUF was proposed using the probability of physical connection between the electrical layers. A few applications of PUF are also presented. PUF is applicable to providing a root of trust for secure SoCs, secure identification and communication of automotive devices and anti-counterfeiting of H/W and S/W IPs.

[Tutorial 2-1] 13:00~14:30

Title : IoT SoC

Wooyoung Choi
Principal Engineer, SoC development, SLSI, Samsung Electronics, Korea


Wooyoung Choi received the B.S. from University of Minnesota, USA in 1999, and the M.S.from KAIST, Korea in 2001. He has been working as a SW engineer for handheld devices for more than 15 years, and has participated in Exynos-i project (SLSI's IoT SoC) since early 2016. He's currently leading SW/ solution for multiple Exynos-i products in SLSI.


As IoT (Internet of Things) market grows rapidly in recent years, IoT SoC (System on Chip) gets equally high expectation from semiconductor industry. In general, IoT SoC can be categorized into three types: 1) things-level, 2) hub-level, and 3) server-level. For things-level IoT SoC, most important HW specs are connectivity (WiFi, BLE, ZigBee, Thread) and cellular (NB1, M1) features along with high security, low power, and low cost. And, its SW competitive factors are open source platform with low memory footprint, developer friendly environment (easy to update, easy to build, easy to debug @ low cost), and availability of some popular IoT frameworks. So far, there is no clear winner in IoT SW platform for this segment. For hub-level IoT SoC, its HW usually requires a much higher computing power as well as various HW IPs (including connectivity and cellular IPs) compared to things-level. Therefore, mobile SoCs (designed for smartphone) can be reused in this segment. And, its SW platform choice is usually Linux or Android, which is a no-brainer. In case of server-level IoT, we are talking about cloud server, and its HW spec requires high-end CPU with extremely high reliability. ARM CPU is not a major player yet in this segment. But, ARM CPU has a great potential here as experts predicted for many years.

[Tutorial 2-2] 14:45~16:15

Title : Modeling NVMe-Enabled SSD Architecture for Full System Simulations

Myoungsoo Jung
Ph.D., Assistant Professor, Yonsei University, Korea


Dr. Myoungsoo Jung is Assistant Professor at Yonsei University. Dr. Jung earned his Ph.D. in Computer Science at Pennsylvania State University and his M.S. in Computer Science from Georgia Institute of Technology, and an M.S. in Embedded System from Korea University in Seoul. Dr. Jung has many years of industry experience, several industrial U.S. patents related to multi-channel SSDs, and approximately sixty technical papers regarding SSD flash firmware and kernel-level file systems. His research has been nominated as best paper from the Institute of Electrical and Electronics Engineers/Association for Computing Machinery (IEEE/ACM) Internal Conference for High Performance Computing, Networking, Storage and Analysis 2013 (SC'13). He received core grant awards from National Science Foundation (NSF) and Department of Energy (DOE), respectively, and the Lawrence Berkeley National Laboratory Award (LBNL) of Excellence. His current research interests include coprocessor architecture (e.g., MIC/GPU), FPGA-based accelerators, advanced computer architecture, and operating systems on emerging non-volatile memory and solid state drive technologies.


There are significant technology shifts in modern flash-based solid state disks (SSDs), and therefore, performance estimations by taking into account a variety of design parameters become more non-trivial. Unfortunately, detailed SSD models often exhibit unreasonably long simulation run-times and requires too much resources to estimate overall performance with diverse configurations. In this tutorial, we will introduce a high-fidelity simulation framework (SimpleSSD), which not only can reconfigure hardware parameters such as flash types, channel frequencies, and different interconnections, but also reconstruct software modules, including address translation, garbage collection and wear-levelling. In contrast to the existing simulators, this brand-new simulator can capture a wide spectrum of storage-internal performance as well as overall system performance by executing diverse CPU benchmarks at user-level. The simulation framework can be downloaded from http://simplessd.camelab.org.

[Tutorial 2-3] 16:30~18:00

Title : Next-Generation Intelligent Computer Systems

Jangwoo Kim
Ph.D., Associate Professor, Seoul National University, Korea


Jangwoo Kim is an associate professor in the Department of Electrical and Computer Engineering at Seoul National University. Before joining SNU, he served as assistant/associate professor for the Department of Computer Science and Engineering at POSTECH. He earned his PhD degree in Computer Engineering from Carnegie Mellon University, and his BS degree in Electrical Engineering and MEng degree in Computer Science all from Cornell University. He was also a CPU/system architect at Sun Microsystems (later acquired by Oracle Corporation) in Santa Clara, USA, to develop UltraSPARC T4 CPUs and low-cost data centers. His research interests include computer architecture, system software, system modeling and brain-inspired intelligent systems.


The next-generation computer systems must satisfy many critical design goals (e.g., performance, energy efficiency, scalability, reliability), while running emerging intelligent applications (e.g., deep learning, neuromorphic applications). However, it is extremely difficult for a system architect to come up with the best server architecture and system software to achieve all the critical design goals in the most cost-effective way. In this talk, I will first introduce emerging intelligent applications and their behaviors. Next, I will describe key limitations of conventional systems in running next-generation intelligent applications. Finally, I will introduce emerging intelligent architecture/system designs to address the issues in the most cost-effective way.

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