Keynote Speeches
Keynote Speech
Forces Shaping the Industry
Chi-Foon Chan
President and co-Chief Executive Officer
Synopsys, Inc.
Abstract
The acceleration of innovation is the driving force in the world's economy. As consumers demand ever faster, lighter, smarter and cheaper solutions, the global design community and semiconductor ecosystem must identify and successfully adopt new strategies to solve the increasingly complex technical and economic challenges. Dr. Chan's presentation will explore these challenges and provide insights into both the new technologies and business strategies required to realize the continued acceleration of innovation.

Biography
As Synopsys' president and co-CEO, Dr. Chi-Foon Chan shares responsibility for crafting vision and strategy, leading the company, and ensuring execution excellence in support of our customers' success. Prior to his May 2012 appointment to president and co-CEO, Dr. Chan served as the company's president and Chief Operation Officer (COO) for 14 years where he led internal operations and worldwide field organizations. Since 1998, Dr. Chan has served on Synopsys' Board of Directors.
Dr. Chan joined Synopsys in 1990 as Vice President of Applications and Services where he served as a Senior Vice President for the Design Tools Group, with responsibility for the business group structure that has continued to grow Synopsys' core EDA business into a principal market position. As General Manager of the DesignWare operations, he established Synopsys' IP business which today represents nearly 25 percent of the company's revenue. He also served as Vice President of Engineering and as Senior Vice President of the Worldwide Field Organization where he advanced global expansion into India, Ireland and China.
In addition to leading Synopsys' entry into the semiconductor IP market, Dr. Chan has personally facilitated several key acquisitions including Avant!, Virage Logic, and most recently, Magma Design Automation.
Previously, Dr. Chan served as General Manager of NEC Corporation's microprocessor group, where he was responsible for marketing all NEC microprocessor devices in North America. Prior to NEC, Dr. Chan was an engineering manager at Intel Corporation.
Dr. Chan serves on the Board of Directors for Hong Kong Silicon Valley advisory group HKSV.COM. He is an Industry Fellow of ISQED and is also a Visiting Professor of Peking University and a member of the Committee 100.
Smart Life by Advanced Semiconductor Technologies
Kyu-Myung Choi
Senior Vice President, Samsung Electronics Co., Ltd.
Abstract
There is no doubt smart life in the future will come by mobile innovation. This mobile innovation becomes true by mobile devices which need high performance, low power, high integration (small form factor), and high communication bandwidth more and more. Fortunately, there has been continuous advancement in process technologies. Recent advancement in 20nm and 14nm process technologies includes 3-dimentional MOSFET called FinFET, DPT(Double Patterning Technology), 3-dimentional chip integration using TSV(Through Silicon Via), and so on. However, these advanced process technologies have been bringing challenges on design infrastructure.
In this talk, I would like to mention the challenges in design infra and the development directions and the current status of resolving design technology challenges. I will talk about those for FinFET, DPT, low power and thermal, 3-dimentional chip integration, and DFM(Design for Manufacturability). Also I will explain how a robust design infra can be prepared efficiently, where the whole idea is diverse collaboration and process & design co-optimization. Finally, Samsung's recent achievements will be introduced briefly.

Biography
Kyu-Myung Choi is Senior Vice President at the System-LSI Division, Samsung Electronics. He is leading the Infrastructure Design Center. His current role in Samsung is to develop the design enablement for all the process nodes and to develop the design methodology for all logic integrated circuits including SOC, LSI and Foundry design. Also, his role is to prepare IPs which consists of Library IP, Mixed-signal IP, Digital IP including High Speed Interface IP, and Multi-media IP.
Since 1985, Kyu-Myung Choi has been with Samsung Electronics, where he has been the team leader for the CAE(Computer Aided Engineering) team and Design Technology team. He has been working for the leader of the Infrastructure Design Center since 2011. Also, he has served as a technical program committee member for many local conferences and IEEE conferences. Kyu-Myung Choi received B.S. and M.S. degrees from Hanyang University, Seoul, Korea in 1983 and 1985, respectively and Ph.D degree in electrical engineering from the University of Pittsburgh, Pennsylvania in 1995.
Pushing the Limits of Embedded Microprocessing
Gideon Intrater
MIPS Technologies, Inc.
Abstract
Moore's Law continues to scale, but due largely to power constraints, adding more transistors no longer means a linear increase in frequency. Today, as we add more transistors, the opportunity lies in increased parallel processing. Doing more work in parallel can keep power consumption to a minimum while increasing overall performance of the system. In many networking and server applications where the workloads are highly parallel, we are seeing multi-core implementations that are able to take advantage of highly parallel processing. But in the consumer world, there are constraints on how far this model can scale. While we are starting to see quad core processors coming to market, not all of the cores are being used efficiently. This is largely because most of today's applications are single-threaded, and the entire system can only run as fast as any sequential load can be processed.

Until software programming catches up with hardware parallelization capabilities, the solution is to build microprocessors which are very efficient in processing the sequential part of an algorithm, while also being able to scale to deal with the parallel part of an application. Mr. Intrater will discuss techniques in building such microprocessors, such as out-of-order execution, branch prediction, very efficient pipelining and others to achieve the highest possible single-threaded performance, along with techniques such as multi-threading which can dramatically improve the throughput when processing parallel workloads.

Biography
Gideon Intrater joined MIPS Technologies in 2010 as Vice President of Product Marketing and Applications, and transitioned to his new role as Vice President of Marketing in November 2011. Mr. Intrater brings more than 20 years of experience in the semiconductor market to this role. Previously, he spent two years as Vice President of Architecture for Symwave, a privately-held supplier of high-performance analog/mixed signal semiconductor solutions for consumer devices. Prior to that, Mr. Intrater was Vice President of Solutions Architecture for MIPS Technologies, having originally joined the company in 1998. Mr. Intrater previously spent 10 years in technical management positions with National Semiconductor Corporation, where he was most recently Director of the Core Technologies Unit. Mr. Intrater earned BSEE and MSEE degrees from the Technion, Israel Institute of Technology, and an MBA from San Jose State University. He holds more than 20 patents.
Development of Human-Machine Interface and Its SoC Solutions for Mobile/Consumer Electronic Systems.
Suki Kim
Korea University
Abstract
People have been used many electronic devices, such as mobile phones, television sets, computers, mentioning a few of them. As the systems get more complicated and multi-functionalized, interfaces between users and machines are becoming more complicated. The needs for easier ways of controlling the equipments are being sought by many engineers and scientists. As many functional systems are integrated into multi-media systems, human-machine interfaces get more complicated and need to find easier way or ways. The solutions have to be convenient and easy to use and meet the cost requirements and system constraints, such as, form factors and power requirements.
By using cognitive and sensory functions, we are trying to find better chip and system solutions: Small form factor, low power, accuracy and friendliness are the basic requirements for the future solutions. To achieve the current and future system requirements, low noise circuit designs, sensitive sensor developments and sophisticated digital processing techniques are the essential part of the solutions.
In this talk, we will review the past of the human-machine interface techniques for the electronic systems, and present the current development status and the foreseeable future technologies. We also show some chip and system solution examples for better understanding.

Biography
Suki Kim is currently Professor in the Department of Electrical and Electronic Engineering at Korea University. He also responsible, running a Fab-less company, called Silicomtech, where the human and machine interface products are being developed and sold.
Suki Kim is holding chairmanship at a steering committee of Korea Semiconductor Conference, which is the largest semiconductor related conference in Korea, being held every year throughout Korea.
He was executive director at Samsung Electronics System LSI Division, responsible for development of the related products. Before coming to Korea, he was manager at Hughes and Honeywell LSI development, being responsible for mixed mode IC design for military uses. Right after getting his Ph.D. degree, he joined AT&T Bell Lab., designing CODEC chips for telephone applications. Prior to AT&T Bell Lab he was semiconductor process development engineer at KIST before going to USA for the advanced degree.
He obtained his Ph.D. degree from the University of Minnesota, Minneapolis, in 1980, Master's degree from the University of Minnesota, Minneapolis, in 1979, Bachelor's degree from Korea University, Seoul, in 1973, all in electrical engineering.