Keynote Speakers

Dr. Jae-hong Park

Executive Vice President of Foundry Design Platform Development, Samsung Electronics, Korea

​Jaehong Park is currently EVP of Engineering at Samsung Electronics where he oversees the Design Platform Development of Samsung Foundry. He received his BS and MS degrees in Electronics Engineering from Seoul National University in 1988 and 1990 respectively, and his Ph.D. degree from the University of Texas at Austin in 1995. Before joining Samsung in 1999, he worked at Motorola, Texas A&M University and IBM in VLSI design and CAD area. Since he joined Samsung, Dr. Park has been responsible for developing various SOCs including MP3 player SOC, DVD player SOC, and Exynos mobile phone AP SOC, and he is now responsible for the Foundry ECO system including EDA, IP, PDK and library, and design service.​

When we define a new technology node, PPAC (Power, Performance, Area, Cost) is an important metric to consider, which determines the benefit of technology migration. As the technology dimension becomes smaller, the silicon area shrinks as well. However, the transistor performance and the metal resistance do not improve at the same pace as the silicon area, which makes improving the power/performance of the SOCs very challenging. In this talk, we will review how we can improve the power/performance of the SOCs by improving the library/IP design and the SOC design methodologies in spite of the fundamental limitation from the technology scaling.​

Keynote Speaker #2 (10:25~11:05, October 22 (Thursday), 2020)

Prof. Massimo Alioto, Ph.D.

ECE-National University of Singapore, Singapore

​Massimo Alioto is a Professor at the ECE Department of the National University of Singapore, where he leads the Green IC group, and is the Director of the Integrated Circuits and Embedded Systems area and the FD-FAbrICS research center on intelligent&connected systems. He held positions at the University of Siena, Intel Labs CRL, University of Michigan Ann Arbor, University of California Berkeley, EPFL - Lausanne.

He is (co)author of 300 publications on journals and conference proceedings, and four books with Springer. His primary research interests include ultra-low power circuits and systems, self-powered integrated systems, near-threshold circuits for green computing, widely energy-scalable integrated systems, circuits for machine intelligence, hardware security, and emerging technologies.

He is the Editor in Chief of the IEEE Transactions on VLSI Systems, Distinguished Lecturer for the IEEE Solid-State Circuits Society, and was Deputy Editor in Chief of the IEEE Journal on Emerging and Selected Topics in Circuits and Systems. Previously, Prof. Alioto was the Chair of the “VLSI Systems and Applications” Technical Committee of the IEEE Circuits and Systems Society (2010-2012), as well as Distinguished Lecturer (2009-2010) and member of the Board of Governors (2015-2020). He served as Guest Editor of numerous journal special issues, Technical Program Chair of several IEEE conferences (ISCAS 2023, SOCC, PRIME, ICECS, VARI, NEWCAS, ICM), and TPC member (ISSCC, ASSCC). Prof. Alioto is an IEEE Fellow.

Wide power-performance adaptation down to nWs has become crucial in always-on nearly real-time and energy-autonomous SoCs that are subject to wide variability in the power availability and the performance target. Wide adaptation is indeed a prerequisite to assure continuous operation in spite of the widely fluctuating energy/power source (e.g., energy harvester), and to grant swift response upon the occurrence of events of interest (e.g., on-chip data analytics), while maintaining extremely low consumption in the common case. These requirements have led to the strong demand of SoCs having an extremely wide performance-power scalability and adaptation, so that they can relentlessly operate without interruption in spite of the highly-uncertain power availability.

In this talk, new directions to drastically extend the performance-power scalability of digital, analog and power management circuits and architectures are presented. Silicon demonstrations of better-than-voltage-scaling adaptation to the workload are illustrated for both the data path (i.e., microarchitecture) and the clock path in the digital sub-system. New directions to achieve full-system coordinated power-performance scaling are also discussed. Silicon demonstrations and trends in the state of the art of battery-light, battery-less and battery-indifferent SoCs are illustrated to quantify the benefits offered by wide power-performance adaptation, identifying opportunities and challenges for the decade ahead. Finally, an always-on mm-scale integrated system that operate uninterruptedly when solely powered by moonlight is demonstrated, paving the way to a new generation of always-on systems with little to no battery.

Keynote Speaker #3 (11:20~12:00, October 22 (Thursday), 2020)

Dr. Thomas Andersen

Heads the Artificial Intelligence and Machine Learning Group, Synopsys, USA

​Dr. Andersen heads the artificial intelligence and machine learning group at Synopsys, where he focuses on developing new technologies in the AI and ML space to automate the future of chip design. He has more than 20 years of experience in the semiconductor and EDA industry. Dr. Andersen started his career at IBM’s TJ Watson Research Center, followed by managing synthesis/place-and-route engineering at Magma Design Automation and Synopsys. He holds a Master’s degree from the University of Stuttgart and a Ph.D. in Computer Engineering from the University of Kaiserslautern in Germany.​

Elias Fallon

Software Engineering Group Director, Cadence

Elias Fallon is currently Engineering Group Director at Cadence Design Systems, a leading Electronic Design Automation company. He has been involved in EDA for more than 20 years from the founding of Neoliner, Inc, which was acquired by Cadence in 2004. Elias was co-Primary Investigator on the MAGESTIC project, funded by DARPA to investigate the application of Machine Learning to EDA for Package/PCB nad Analog IC. Elias also leads an innovation incubation team within the Custom IC R&D group as well as other traditional EDA product teams. Beyond his work developing electronic design automation tools, he has led software quality improvement initiatives within Cadence, partnering with the Carnegie Mellon Software Engineering Institute. Elias graduated from Carnegie Mellon University with an M.S. and B.S. in Electrical and Computer Engineering. Elias, his wife and two children live north of Pittsburgh, PA. https://www.linkedin.com/in/elias-fallon/​

​Electronic Design Automation software has delivered semiconductor design productivity improvements for decades. The next leap in productivity will come from the addition of machine learning techniques to the toolbox of computational software capabilities employed by EDA developers. Recent research and development into machine learning for EDA point to clear patterns for how it impacts EDA tools, flows, and design challenges. This talk will detail the application of machine learning "inside" EDA tools and "outside" tool flows. The convergence of industry trends such as intelligent networks, ans intelligent edge and cloud compute along with AI/ML techniques lead to an exciting future for our industry.

Keynote Speaker #5 (11:10~11:50, October 23 (Friday), 2020)